1. Field of the Invention
The present invention relates to a semiconductor chip having a pad used for testing an internal circuit.
2. Description of the Related Art
In a process of manufacturing a semiconductor device, a large number of circuit elements are formed on a semiconductor wafer, and a plurality of semiconductor chips having internal circuits are cut out from the semiconductor wafer. The internal circuit includes a memory circuit, a fuse circuit and a CPU. The semiconductor chip is test by a tester having a probe card and a measuring circuit, to test the electric property of the internal circuit.
As the result of the test, the semiconductor chip of good quality is shipped. In the semiconductor chip of the defective semiconductor chips which has a defect in a memory circuit, a redundancy process is carried out to replace a defective memory cell with a redundant memory cell by using a fuse circuit. Thus, the defective semiconductor chip is changed to a good quality semiconductor chip. Defective semiconductor chips are discarded.
A semiconductor chip has a plurality of pads. When the semiconductor chip is tested, the pads on the semiconductor chip are probed with a probe card. In this case, the probed pads are not required to be all of the pads in the semiconductor chip. Preferably, the necessarily minimum number of the pads is desirable. For this reason, when the probed pad is defined as a probing pad P0 and the non-probed pad is defined as a non-probing pad P1, the operation check of the internal circuit for the probing pad P0 is carried out by probing the probing pad P0, and the operation check of the internal circuit for the non-probing pad P1 is carried out by using a test mode and then probing the probing pad P0. This will be described with reference to FIG. 1.
FIG. 1 shows the configuration of a semiconductor chip 101. The semiconductor chip 101 contains an internal data bus 160, a test interface circuit 140, a non-test interface circuit 141, selector circuits 150 and 151 and a test circuit 190 in addition to the probing pad P0 and the non-probing pad P1. Also, an internal circuit 180 of the semiconductor chip 101 includes a memory circuit (not shown), a fuse circuit (not shown) and a CPU (Central Processing Unit) (not shown). The internal circuit is connected to the internal data bus 160. The internal data bus 160 includes a test internal bus and a non-test internal bus. The test internal bus includes an internal input bus N0 and an internal output bus N0′, and the non-test internal bus includes an internal input bus N1 and an internal output bus N1′.
The test interface circuit 140 contains an input circuit 110, an input protection resistor 120 and an output circuit 130. The input circuit 110 is connected to the input protection resistor 120 and the selector circuit 150. The input protection resistor 120 is connected to the probing pad P0. The output circuit 130 is connected to the selector circuit 150, the input protection resistor 120 and the probing pad P0. The non-test interface circuit 141 contains an input circuit 111, an input protection resistor 121 and an output circuit 131. The input circuit 111 is connected to the input protection resistor 121 and the selector circuit 151. The input protection resistor 121 is connected to the non-probing pad P1. The output circuit 131 is connected to the selector circuit 151, the input protection resistor 121 and the non-probing pad P1.
A test apparatus 102 includes the probe card and measuring device, as described above. The probing pad P0 is probed with the probe card. For example, the test apparatus 102 checks the memory circuit of the internal circuit 180 for a write operation and a read operation. Also, the test circuit 190 sends a test mode signal T100 indicating a low level to the selector circuits 150 and 151, when the test apparatus 102 carries out the operation check of the internal circuit for the probing pad P0. In this case, the selector circuit 150 connects the input circuit 110 and the internal input bus N0 and connects the output circuit 130 and the internal output bus N0′. The test circuit 190 sends the test mode signal T100 indicating a high level to the selector circuits 150 and 151, when the test apparatus 102 carries out the operation check of the internal circuit for the non-probing pad P1. In this case, the selector circuit 151 connects the input circuit 110 and the internal input bus N1 through the selector circuit 150 and connects the output circuit 130 and the internal output bus N1′ through the selector circuit 150. The test apparatus 102 outputs a probe signal such as a clock signal, to check the operation of the internal circuit. At this time, the test apparatus 102 checks the operation of the internal circuit for (A) the probing pad P0 and checks the operation of the internal circuit for (B) the non-probing pad P1. This will be described by using FIG. 1.
The operation check in the (A) case will be described below.
The test apparatus 102, when checking the operation of the internal circuit for the probing pad P0, sends a first probe signal to the probing pad P0. For example, the first probe signal indicates the high level in a first period and indicates the low level in a next period. The first probe signal of the high level includes a write command and a write data as a test data, and the first probe signal of the low level includes a read command.
Also, the test circuit 190 sends the test mode signal T100 of the low level to the selector circuits 150 and 151. Since the test mode signal T100 indicates the low level, the selector circuit 150 connects the input circuit 110 and the internal input bus N0 and connects the output circuit 130 and the internal output bus N0′.
At first, the test apparatus 102 sends the write command including an address to the probing pad P0. The input circuit 110 of the test interface circuit 140 receives the write command sent to the probing pad P0 through the input protection resistor 120 and outputs the write command through the selector circuit 150, the internal input bus N0 and the internal data bus 160 to the memory circuit of the internal circuit 180.
Next, the test apparatus 102 sends the write data to the probing pad P0. The input circuit 110 of the test interface circuit 140 receives the write data sent to the probing pad P0 through the input protection resistor 120 and outputs the write data through the selector circuit 150, the internal input bus N0 and the internal data bus 160 to the memory circuit of the internal circuit 180. The write data is written to the memory cell corresponding to the address included in the write command, among the plurality of memory cells of the memory circuit in the internal circuit 180.
Next, the test apparatus 102 sends the read command including the address to the probing pad P0. The input circuit 110 of the test interface circuit 140 receives the read command sent to the probing pad P0 through the input protection resistor 120 and outputs the read command through the selector circuit 150, the internal input bus N0 and the internal data bus 160 to the memory circuit in the internal circuit 180. At this time, the stored data is read out from the memory cell corresponding to the address included in the read command among the plurality of memory cells of the memory circuit in the internal circuit 180. The read data is sent from the internal circuit 180 through the internal data bus 160, the internal output bus N0′ and the selector circuit 150 to the test interface circuit 140. The output circuit 130 of the test interface circuit 140 outputs the read data through the probing pad P0 to the test apparatus 102.
Consequently, the test apparatus 102 compares the write data and the read data as the test result in the first probe signal, and if they are coincident with each other, generates the test result indicating the good quality, and if they are not coincident with each other, generates the test result indicating the bad quality. In this way, according to the conventional semiconductor chip, the test apparatus 102 can check the operation of the internal circuit for the probing pad P0.
The operation check in the (B) case will be described below.
The test apparatus 102, when checking the operation of the internal circuit for the non-probing pad P1, sends a second probe signal to the probing pad P0. For example, the second probe signal indicates the high level in the first period and indicates the low level in the next period. The second probe signal of the high level includes the write command and the write data, and the second probe signal of the low level includes the read command. Also, the test circuit 190 sends a test mode signal T100 of the high level to the selector circuits 150 and 151. Since the test mode signal T100 indicates the high level, the selector circuit 151 connects the input circuit 110 and the internal input bus N1 and connects the output circuit 130 and the internal output bus N1′ through the selector circuit 150.
At first, the test apparatus 102 sends the write command including the address to the probing pad P0. The input circuit 110 of the test interface circuit 140 receives the write command sent to the probing pad P0 through the input protection resistor 120 and outputs the write command through the selector circuits 150 and 151, the internal input bus N1 and the internal data bus 160 to the memory circuit of the internal circuit 180.
Next, the test apparatus 102 sends the write data to the probing pad P0, The input circuit 110 of the test interface circuit 140 receives the write data sent to the probing pad P0 through the input protection resistor 120 and outputs the write data through the selector circuits 150 and 151, the internal input bus N1 and the internal data bus 160 to the memory circuit of the internal circuit 180. The write data is written to the memory cell corresponding to the address included in the write command among the plurality of memory cells of the memory circuit in the internal circuit 180.
Next, the test apparatus 102 sends the read command including the address to the probing pad P0. The input circuit 110 of the test interface circuit 140 receives the read command sent to the probing pad P0 through the input protection resistor 120 and outputs the read command through the selector circuits 150 and 151, the internal input bus N1 and the internal data bus 160 to the memory circuit in the internal circuit 180. At this time, the read data is read from the memory cell corresponding to the address included in the read command among the plurality of memory cells of the memory circuit in the internal circuit 180. The read data is sent from the memory circuit in the internal circuit 180 through the internal data bus 160, the internal output bus N1′ and the selector circuits 151, 150 to the test interface circuit 140. The output circuit 130 of the test interface circuit 140 outputs the read data through the probing pad P0 to the test apparatus 102.
Consequently, the test apparatus 102 compares the write data and the read data as the test result in the second probe signal, and if they are coincident with each other, generates the test result indicating the good quality, and if they are not coincident with each other, generates the test result indicating the bad quality. In this way, according to the conventional semiconductor chip, the test apparatus 102 can check the operation of the internal circuit for the non-probing pad P1.
However, in the conventional semiconductor chip, although the defect in the test interface circuit 140 can be tested, it is impossible to test a defect in the non-test interface circuit 141. When the test apparatus 102 checks the operation of the internal circuit corresponding to the probing pad P0, if the write data and the read data are coincident with each other, this indicates that the test interface circuit 140 is normal. Thus, it is possible to test the defect in the test interface circuit 140. On the other hand, when the test apparatus 102 checks the operation of the internal circuit for the non-probing pad P1, even if the write data and the read data are coincident with each other, this does not indicate whether or not the non-test interface circuit 141 is normal. Therefore, it is impossible to test the defect in the non-test interface circuit 141.
In conjunction with the above description, semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P2000-124278A) in which a scribe line having no influence on a chip size is used to improve an integration rate, a small number of pins are used to efficiently test a wafer, and the test time of the wafer is reduced. This semiconductor device is intended to collectively test a plurality of semiconductor chips formed on the semiconductor wafer. A cut region of the semiconductor chip contains a wafer test pad for making the test pins of adjacent semiconductor chips in contact with each other and probing them, a controller for determining whether or not the semiconductor chip connected to the wafer test pad is normal; and a control pad for inputting a control signal to control the controller. The controller carries out a comparison test of an expectation value, for the respective semiconductor chips connected adjacently to the wafer test pad, in accordance with the control signal inputted to the control pad, and judges whether or not the semiconductor chip is normal, in accordance with whether the expectation value is matched or unmatched.
Also, Japanese Laid Open Patent Application (JP-P2004-85526A) describes a semiconductor device, which is used for a system-in-package and attains an output buffer circuit that can drive an output pad with an optimally driving power, in a usual operation mode and a test operation mode. This semiconductor device has first and second output buffers coupled to the output pad. The first output buffer is activated in the usual operation mode, and set to an output high impedance state in the test operation mode, and drives the output pad with a first driving power in accordance with an inner signal on the activation. The second output buffer is activated in the test operation mode, and set to the output high impedance state in the usual operation mode, and drives the output pad with a second driving power greater than the first driving power in accordance with the inner signal at the time of the activation.
Also, Japanese Laid Open Patent Application (JP-P2001-210685A) describes a testing system which can test a semiconductor chip in a short time without using any expensive tester. The testing system carries out an electric test of the semiconductor chip formed on a semiconductor wafer. This is provided with a probe card, a test circuit and a controller. On the probe card, a conductive needle is placed correspondingly to the arrangement of electrode pads in the semiconductor chip, and it is connected to the test circuit. The test circuit is provided in the probe card and tests the semiconductor chip on the basis of a program. The controller rewrites the program in the test circuit and stores the test result outputted from the test circuit.